Screen LibrarySystem-level validation : high-level modeling and directed test generation techniques /
This book covers state-of-the art techniques for high-level modeling and validation of complex hardware/software systems, including those with multicore architectures. Readers will learn to avoid time-consuming and error-prone validation from the comprehensive coverage of system-level validation, in...
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| Main Authors: | |
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| Corporate Authors: | |
| Published: |
Springer,
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| Publisher Address: | New York, NY : |
| Publication Dates: | 2013. |
| Literature type: | eBook |
| Language: | English |
| Subjects: | |
| Online Access: |
http://dx.doi.org/10.1007/978-1-4614-1359-2 |
| Summary: |
This book covers state-of-the art techniques for high-level modeling and validation of complex hardware/software systems, including those with multicore architectures. Readers will learn to avoid time-consuming and error-prone validation from the comprehensive coverage of system-level validation, including high-level modeling of designs and faults, automated generation of directed tests, and efficient validation methodology using directed tests and assertions. The methodologies described in this book will help designers to improve the quality of their validation, performing as much validation as possible in the early stages of the design, while reducing the overall validation effort and cost. |
| Carrier Form: | 1 online resource (xxi, 247 pages) |
| Bibliography: | Includes bibliographical references and index. |
| ISBN: |
9781461413592 (electronic bk.) 1461413591 (electronic bk.) |
| Index Number: | TK7895 |
| CLC: | TP311.521 |
| Contents: |
Modeling and specification of soC designs -- Automated generation of directed tests -- Functional test compaction -- Property clustering and learning techniques -- Decision ordering based learning techniques -- Synchronized generation of directed tests -- Test generation using design and property decompositions -- Learning-Oriented property decomposition approaches -- Directed test generation for multicore architectures -- Test generation for cache coherence validation -- Reuse of system-Level validation efforts -- Conclusions. |