Screen LibrarySeparation logic for high-level synthesis /
This book presents novel compiler techniques, which combine a rigorous mathematical framework, novel program analyses and digital hardware design to advance current high-level synthesis tools and extend their scope beyond the industrial?state of the art?. Implementing computation on customised digit...
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| Main Authors: | |
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| Published: |
Springer,
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| Publisher Address: | Cham, Switzerland : |
| Publication Dates: | [2017] |
| Literature type: | Book |
| Language: | English |
| Series: |
Springer theses,
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| Subjects: | |
| Summary: |
This book presents novel compiler techniques, which combine a rigorous mathematical framework, novel program analyses and digital hardware design to advance current high-level synthesis tools and extend their scope beyond the industrial?state of the art?. Implementing computation on customised digital hardware plays an increasingly important role in the quest for energy-efficient high-performance computing. Field-programmable gate arrays (FPGAs) gain efficiency by encoding the computing task into the chip?s physical circuitry and are gaining rapidly increasing importance in the processor market, especially after recent announcements of large-scale deployments in the data centre. This is driving, more than ever, the demand for higher design entry abstraction levels, such as the automatic circuit synthesis from high-level languages (high-level synthesis). The techniques in this book apply formal reasoning to high-level synthesis in the context of demonstrably practical applications.<. |
| Item Description: | "Doctoral thesis accepted by Imperial College London, UK." |
| Carrier Form: | xix, 132 pages : illustrations (some color), forms ; 24 cm. |
| Bibliography: | Includes bibliographical references. |
| ISBN: |
9783319532219 (hardback) : 3319532219 (hardback) |
| Index Number: | QA76 |
| CLC: | TP338.6 |
| Call Number: | TP338.6/W788 |
| Contents: | 1. Introduction -- 2. High-level Synthesis of Dynamic Data Structures -- 3. Background -- 4. Heap Partitioning and Parallelisation -- 5. Custom Multi-Cache Architectures -- 6. Conclusion -- Bibliography -- Appendices. |