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Nano-CMOS design for manufacturability robust circuit and physical design for sub-65 nm technology nodes /

"Nano-CMOS Design for Manufacturability examines the challenges that design engineers face in the nano-scaled era, such as exacerbated effects and the proven design for manufacturability (DFM) methodology in the midst of increasing variability and design process interactions. In addition to dis...

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Bibliographic Details
Group Author: Wong, Ban P., 1953
Published:
Literature type: Electronic eBook
Language: English
Subjects:
Metal oxide semiconductors, Complementary > Design and construction
Integrated circuits > Design and construction
Nanoelectronics
TECHNOLOGY & ENGINEERING > Electronics > Circuits > VLSI & ULSI
TECHNOLOGY & ENGINEERING > Electronics > Circuits > Logic
COMPUTERS > Logic Design
Electronic books
Online Access: http://onlinelibrary.wiley.com/book/10.1002/9780470382820
Summary: "Nano-CMOS Design for Manufacturability examines the challenges that design engineers face in the nano-scaled era, such as exacerbated effects and the proven design for manufacturability (DFM) methodology in the midst of increasing variability and design process interactions. In addition to discussing the difficulties brought on by the continued dimensional scaling in conformance with Moore's law, the authors also tackle complex issues in the design process to overcome the difficulties, including the use of a functional first silicon to support a predictable product ramp. Moreover, they intr
Carrier Form: 1 online resource (xv, 385 pages) : illustrations
Bibliography: Includes bibliographical references and index.
ISBN: 9781615831753 (electronic bk.)
1615831754 (electronic bk.)
9780470382820
0470382821
9780470382813 (electronic bk.)
0470382813 (electronic bk.)
Index Number: TK7871
CLC: TN432.02
Contents: 1. Introduction. 1.1 DFM -- Value proposition. 1.2 Deficiencies in Boolean-based Design Rules in the sub-wavelength regime [6].1.3 Impact of Variability on Yield and Performance. 1.4 The industry challenge -- disappearing process window. 1.5 Mobility enhancement techniques -- a new source of variability induced by design process interaction. 1.6 Design dependency of chip surface topology. 1.7 Newly exacerbated narrow width effect in nano-CMOS nodes. 1.8 Well proximity effect. 1.9 Scaling beyond 65nm drives the need for model based DFM solutions. 1.10 Summary. PART 1: NEWLY EXACERBATED EFFECT

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