Robust SRAM designs and analysis /

This book provides a guide to Static Random Access Memory (SRAM) bitcell design and analysis to meet the nano-regime challenges for CMOS devices and emerging devices, such as Tunnel FETs. Since process variability is an ongoing challenge in large memory arrays, this book highlights the most popular...

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Bibliographic Details
Main Authors: Singh, Jawar
Corporate Authors: SpringerLink (Online service)
Group Author: Mohanty, Saraju P.; Pradhan, Dhiraj K.
Published: Springer,
Publisher Address: New York, NY :
Publication Dates: 2013.
Literature type: eBook
Language: English
Subjects:
Online Access: http://dx.doi.org/10.1007/978-1-4614-0818-5
Summary: This book provides a guide to Static Random Access Memory (SRAM) bitcell design and analysis to meet the nano-regime challenges for CMOS devices and emerging devices, such as Tunnel FETs. Since process variability is an ongoing challenge in large memory arrays, this book highlights the most popular SRAM bitcell topologies (benchmark circuits) that mitigate variability, along with exhaustive analysis. Experimental simulation setups are also included, which cover nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis. Emphasis is placed throughout the book on the various trade-offs for achieving a best SRAM bitcell design.Provides a complete and concise introduction to SRAM bitcell design and analysis; Offers techniques to face nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis;Includes simulation set-ups for extracting different design metrics for CMOS technology and emerging devices;Emphasizes different trade-offs for achieving the best possible SRAM bitcell design.
Carrier Form: 1 online resource
Bibliography: Includes bibliographical references and index.
ISBN: 9781461408185 (electronic bk.)
1461408180 (electronic bk.)
Index Number: TK7895
CLC: TP333.8
Contents: Introduction to SRAM --
Design Metrics of SRAM Bitcell --
Single-Ended SRAM Bitcell Design --
2-Port SRAM Bitcell Design --
SRAM Bitcell Design Using Unidirectional Devices --
NBTI and Its Effect on SRAM.