Screen LibraryClosing the power gap between ASIC & custom：tools and techniques for low power design
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| Main Authors: | |
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| Corporate Authors: | |
| Group Author: | |
| Published: |
Springer Science+Business Media,
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| Publisher Address: | New York |
| Publication Dates: | c2007. |
| Literature type: | Book |
| Language: | English |
| Subjects: | |
| Online Access: |
http://dx.doi.org/10.1007/978-0-387-68953-1 |
| Carrier Form: | xii, 384 p.: ill. ; 24 cm. |
| ISBN: |
9780387689531 (electronic bk.) 0387689532 (electronic bk.) |
| Index Number: | TN430 |
| CLC: | TN430.2 |
| Contents: |
Includes bibliographical references and index. Ch. 1. Introduction -- Ch. 2. Overview of the factors affecting the power consumption -- Ch. 3. Pipelining to reduce the power -- Ch. 4. Voltage sealing -- Ch. 5. Methodology to optimize energy of computation for SOCs -- Ch. 6. Linear programming for gate sizing -- Ch. 7. Linear programming for multi-Vth and multi-Vdd assignment -- Ch. 8. Power optimization using multiple supply voltages -- Ch. 9. Placement for power optimization -- Ch. 10. Power gating design automation -- Ch. 11. Verification for multiple supply voltage designs -- Ch. 12. Winning the power struggle in an uncertain era -- Ch. 13. Pushing ASIC performance in a power envelope -- Ch. 14. Low power ARM 1136JF-S design. |