Screen LibraryDesign and test technology for dependable systems-on-chip /
Covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC).
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| Corporate Authors: | |
|---|---|
| Group Author: | ; ; |
| Published: |
IGI Global,
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| Publisher Address: | Hershey, Pa. : |
| Publication Dates: | 2011. |
| Literature type: | eBook |
| Language: | English |
| Subjects: | |
| Online Access: |
http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/978-1-60960-212-3 |
| Summary: |
Covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC). |
| Carrier Form: | PDFs (1 v.) : illustrations |
| Bibliography: | Includes bibliographical references. |
| ISBN: | 9781609602147 (ebook) |
| Access: | Restricted to subscribers or individual electronic text purchasers. |
| Index Number: | TK7895 |
| CLC: | TN43 |
| Contents: |
1. System-level design of NoC-based dependable embedded systems / Mihkel Tagel, Peeter Ellervee, Gert Jervan -- 2. Synthesis of flexible fault-tolerant schedules for embedded systems with soft and hard timing constraints / Viacheslav Izosimov ... et al. -- 3. Optimizing fault tolerance for multi-processor system-on-chip / Dimitar Nikolov ... et al. -- 4. Diagnostic modeling of digital systems with multi-level decision diagrams / Raimund Ubar ... et al. -- 5. Enhanced formal verification flow for circuits integrating debugging and coverage analysis / Daniel Grosse, G orschwin Fey, Rolf Drechsler -- 6. Advanced technologies for transient faults detection and compensation / Matteo Reorda, Luca Sterpone, Massimo Violante -- 7. Memory testing and self-repair / M aria Fischerov a, Elena Gramatov a -- 8. Fault-tolerant and fail-safe design based on reconfiguration / Hana Kubatova, Pavel Kubalik -- 9. Self-repair technology for global interconnects on SoCs / Daniel Scheit, Heinrich Vierhaus -- 10. Built-in self repair for logic structures / Tobias Koal, Heinrich Vierhaus -- 11. Self-repair by program reconfiguration in VLIW processor architectures / Mario Sch olzel, Pawel Pawlowski, Adam Dabrowski -- 12. Fault simulation and fault injection technology based on SystemC / Silvio Misera, Roberto Urban -- 13. High-level decision diagram simulation for diagnosis and soft-error analysis / Jaan Raik ... et al. -- 14. High-speed logic level fault simulation / Raimund Ubar, Sergei Devadze -- 15. Software-based self-test of embedded microprocessors / Paolo Bernardi ... et al. -- 16. SoC self test based on a test-processor / Tobial Koal, Rene Kothe, Heinrich Vierhaus -- 17. Delay faults testing / Marcel Bal a z, Roland Dobai, Elena Gramatov a -- 18. Low power testing / Zdenek Kot asek, Jaroslav Skarvada -- 19. Thermal-aware SoC test scheduling / Zhiyuan He, Zebo Peng, Petru Eles -- 20. Study on combined test-data compression and test planning for testing of modular SoCs / Anders Larsson ... et al. -- 21. Reduction of the transferred test data amount / Ondrej Nov ak -- 22. Sequential test set compaction in LFSR reseeding / Artur Jutman, Igor Aleksejev, Jaan Raik. |