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Stress management for 3D ICs using through silicon vias：International Workshop[s] on Stress Management for 3D ICs Using Through Silicon Vias, Albany, NY, U.S.A, March 16, 2010, San Francisco, CA, U.S.A., July 13, 2010, Dresden, Germany, October 20, 2010

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Bibliographic Details
Corporate Authors: International Workshop on Stress Management for 3D ICs Using Through Silicon Vias (2010 Albany, N.Y; International Workshop on Stress Management for 3D ICs Using Through Silicon Vias (2010 Dresden, Germany); International Workshop on Stress Management for 3D ICs Using Through Silicon Vias (2010 San Francisco, Calif.)
Group Author: Zschech Ehrenfried
Published: American Institute of Physics,
Publisher Address: Melville, N.Y.
Publication Dates: 2011.
Literature type: Book
Language: English
Series: AIP conference proceedings ; 1378
Subjects:
Stress relaxation > Simulation methods
Strains and stresses > Simulation methods
Strains and stresses > Measurement
Three-dimensional integrated circuits > Design and construction
Carrier Form: vi, 175 p.: ill. ; 24 cm.
ISBN: 9780735409385 (hbk.)
0735409382
Index Number: B849
CLC: B849
Call Number: B849/I618/2010
Contents: Includes bibliographical references and index.
White papers -- Multi-scale modeling -- Multi-scale materials parameters -- Multi-scale stress characterization -- ISV : process characterization and failure analysis.

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