Stress management for 3D ICs using through silicon vias：International Workshop[s] on Stress Management for 3D ICs Using Through Silicon Vias, Albany, NY, U.S.A, March 16, 2010, San Francisco, CA, U.S.A., July 13, 2010, Dresden, Germany, October 20, 2010

Corporate Authors: International Workshop on Stress Management for 3D ICs Using Through Silicon Vias (2010 Albany, N.Y; International Workshop on Stress Management for 3D ICs Using Through Silicon Vias (2010 Dresden, Germany); International Workshop on Stress Management for 3D ICs Using Through Silicon Vias (2010 San Francisco, Calif.)
Group Author: Zschech Ehrenfried
Published: American Institute of Physics,
Publication Dates: 2011.
Call Number: B849/I618/2010