Screen LibraryThree-dimensional integrated circuit design /
With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. This is due primarily to the inevitable increase in the distance among circuit...
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| Main Authors: | |
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| Corporate Authors: | |
| Group Author: | |
| Published: |
Morgan Kaufmann,
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| Publisher Address: | Amsterdam ; Boston : |
| Publication Dates: | 2009. |
| Literature type: | eBook |
| Language: | English |
| Series: |
The Morgan Kaufmann series in systems on silicon
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| Subjects: | |
| Online Access: |
http://www.sciencedirect.com/science/book/9780123743435 |
| Summary: |
With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. This is due primarily to the inevitable increase in the distance among circuit elements and interconnect design solutions have become the greatest determining factor in overall performance. |
| Carrier Form: | 1 online resource (xv, 309 pages) : illustrations. |
| Bibliography: | Includes bibliographical references (pages 289-303) and index. |
| ISBN: |
9780123743435 0123743435 9780080921860 0080921868 |
| Index Number: | TK7874 |
| CLC: | TN47 |
| Contents: | Chapter 1. Introduction -- Chapter 2. Manufacturing of 3-D Packaged Systems -- Chapter 3. 3-D Integrated Circuit Fabrication Technologies -- Chapter 4. Interconnect Prediction Models -- Chapter 5. Physical Design Techniques for 3-D ICs -- Chapter 6. Thermal Management Techniques -- Chapter 7. Timing Optimization for Two-Terminal Interconnects -- Chapter 8. Timing Optimization for Multi-Terminal Interconnects -- Appendix A: Enumeration of Gate Pairs in a 3-D IC --Appendix B: Formal Proof of Optimum Single Via Placement -- Appendix C: Proof of the Two-Terminal Via Placement Heuristic -- Append |