Screen LibraryConstraining designs for synthesis and timing analysis a practical guide to synopsys design constraints (SDC) /
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| Literature type: | Electronic eBook |
| Language: | English |
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| Online Access: |
http://dx.doi.org/10.1007/978-1-4614-3269-2 |
| Carrier Form: | 1 online resource (xxvii, 226 p.) |
| Bibliography: | Includes bibliographical references and index. |
| ISBN: |
9781461432692 (electronic bk.) 1461432693 (electronic bk.) |
| Index Number: | TK7895 |
| CLC: | TP302.1 |
| Contents: |
Introduction -- Synthesis Basics -- Timing Analysis and Constraints -- SDC Extensions Through Tcl -- Clocks -- Generated Clocks -- Clock Groups -- Other Clock Characteristics -- Port Delays -- Completing Port Constraints -- False Paths -- Multi Cycle Paths -- Combinational Paths -- Modal Analysis -- Managing Your Constraints -- Miscellaneous SDC s Commands -- XDC: Xilinx Extensions to SDC. |