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VLSI test principles and architectures : design for testability /

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of indu...

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Bibliographic Details
Corporate Authors: Elsevier Science & Technology
Group Author: Wang, Laung-Terng; Wu, Cheng-Wen, EE Ph. D; Wen, Xiaoqing
Published: Elsevier Morgan Kaufmann Publishers,
Publisher Address: Amsterdam ; Boston :
Publication Dates: 2006.
Literature type: eBook
Language: English
Series: The Morgan Kaufmann series in systems on silicon
Subjects:
Integrated circuits > Very large scale integration > Testing
Integrated circuits > Very large scale integration > Design
Circuits inte gre s a tre s grande e chelle > Essais
Circuits inte gre s a tre s grande e chelle > Conception et construction
TECHNOLOGY & ENGINEERING > Electronics > Circuits > VLSI & ULSI
TECHNOLOGY & ENGINEERING > Electronics > Circuits > Logic
COMPUTERS > Logic Design
Circuitos integrados vlsi
Testen
VLSI
Integrated circuits / Very large scale integration / Testing
Integrated circuits / Very large scale integration / Design
Electronic books
Online Access: http://www.sciencedirect.com/science/book/9780123705976
Summary: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Lecture slides and exercise solutions for all chapters are now available. Instructors are also eligibl
Carrier Form: 1 online resource (xxx, 777 pages) : illustrations.
Bibliography: Includes bibliographical references and index.
ISBN: 9780080474793
0080474799
Index Number: TK7874
CLC: TN47
Contents: Design for testability / Laung-Terng (L.-T.) Wang, Xiaoqing Wen, and Khader S. Abdel-Hafez -- Logic and fault simulation / Jiun-Lang Huang, James C.-M. Li, and Duncan M. (Hank) Walker -- Test generation / Michael S. Hsiao -- Logic built-in self-test / Laung-Terng (L.-T.) Wang -- Test compression / Xiaowei Li, Kuen-Jong Lee, and Nur A. Touba -- Logic diagnosis / Shi-Yu Huang -- Memory testing and built-in self-test / Cheng-Wen Wu -- Memory diagnosis and built-in self-repair / Cheng-Wen Wu -- Boundary scan and core-based testing / Kuen-Jong Lee -- Analog and mixed-signal testing / Chauchin Su

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